Arockia Suresh has extensive experience in the field of engineering, with a focus on design and verification. Beginning a career as an ASIC Verification Engineer at SmartDV Technologies India Private Limited from July 2014 to August 2018, Arockia specialized in developing Verification IP (VIP) for various AMBA protocols including AXI, AHB, APB, ACE, and CHI5. Subsequently, Arockia advanced to lead roles at Cadence Design Systems as a Lead Design Engineer from December 2020 to April 2022 and has been working as a Full Chip Design Verification Engineer at Google since May 2022. Prior experience includes a position as a DV Engineer at Microchip Technology Inc. from August 2018 to December 2020. Arockia holds a Bachelor of Engineering in Electronics and Communications Engineering from Velammal Engineering College, completed between 2010 and 2014.
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