Ashwinya M.

Ashwinya M. is an experienced ASIC Design Engineer currently at Google since February 2022. Prior experience includes roles as a SoC RTL Design Engineer at Intel Corporation from December 2017 to March 2022, and as a Senior RTL Design Engineer at Oracle from July 2013 to November 2017, focusing on Power Management within the SPARC Processor project. Ashwinya has expertise in RTL Design and Microarchitecture, leading R&D for power management strategies and contributing to post-silicon validation for various processors. Ashwinya holds a Master’s degree in Electrical Engineering, specializing in VLSI and Computer Architecture from the University of Southern California, and a Bachelor's degree in Electrical and Electronics Engineering from Government College of Technology, Coimbatore, India.