Asila Nahas is a highly skilled engineering professional with extensive experience in verification and software engineering. Beginning a career as a Senior Design Verification Engineer at Intel Corporation from March 2009 to April 2014, Asila developed expertise in verification flows and testbench development. After transitioning to Cadence Design Systems, Asila served as a Principal Software Engineer from July 2014 to April 2019, leading the development of Verification IP software for advanced protocols. Promoted to Senior Software Engineering Manager at Cadence from May 2019 to August 2020, Asila managed an international team focused on CXL and DisplayPort products. Currently, Asila is the Software Engineering Manager at Google, overseeing the Verification IP portfolio aligned with the Intelligent System Design Strategy, including flagship products like DisplayPort Verification IP. Asila holds a Master of Science in Electrical Engineering from the University of Southern California and a Bachelor of Technology in Electrical and Electronics Engineering from the National Institute of Technology Calicut.
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