Chao Zhang, PhD, has a strong background in engineering and research, with significant experience in the semiconductor and memory technologies industries. From November 2018 to February 2021, Chao worked as a Sr. Device Engineer at Yangtze Memory Technologies, focusing on optimizing 3D NAND flash memory arrays. Following this role, Chao served as a Staff Engineer at Intel Corporation from April 2022 to November 2023, where responsibilities included the characterization and optimization of 3D NAND devices. Previous positions included Clean Room Engineer at Tsinghua University, Graduate Research Assistant at Rice University, and Research and Development Engineer at Syzygy Plasmonics. Chao holds a PhD in Electrical and Electronics Engineering and a Master of Science from Rice University, as well as a BS in Physics from Tsinghua University. Currently, Chao is a Display Electrical Engineer at Google.
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