Ching-Han Tsai

Ching-Han Tsai is an accomplished engineering professional currently serving as Sr. Manager of Silicon Architecture at Google, where responsibilities include leading the design, integration, and validation of MM/ML IPs for Tensor SOCs in Taipei. Previously, Ching-Han held significant roles at Ubiquiti Networks as Product Line Manager, successfully launching the LTU product line, and at NVIDIA as Senior Systems Architect, managing the Tegra X1 chip architecture. Additional experience includes positions at Ablaze Wireless, Marvell, Mobilic, and High Bandwidth Access, spanning architecture, design, and team leadership in various advanced technologies. Ching-Han earned a Ph.D. in Electrical and Computer Engineering from the University of Illinois Urbana-Champaign and a B.S. in Electrical Engineering from National Taiwan University.