Deepak Singhal

Deepak Singhal is an experienced design engineer with a robust background in RTL low power design and chip-level architectures. Deepak began the career at Tata Consultancy Services as a Senior Design Engineer, followed by a role as Lead Designer at Mentor Graphics, where RTL design and development took place. At Xilinx, Deepak contributed as a Senior Design Engineer, focusing on power optimization in the Vivado tool. Deepak further honed expertise as a Design Engineer at NXP India, leading SOC front-end efforts and platform architecture. Subsequently, a position as a Staff Engineer at Qualcomm involved designing a Global Clock Controller. Currently, Deepak serves as a Design Engineer at Google, leading efforts in Fabric IP and subsystem architecture. Deepak holds a Master of Technology degree in Electrical, Electronics and Communications Engineering from the ABV-Indian Institute of Information Technology and Management in Gwalior, India.