Dima Roginsky is an accomplished engineering professional with extensive experience in VLSI and ASIC design. Beginning a career as a VLSI Engineer at Siverge Networks from May 2010 to June 2013, Dima transitioned to SatixFy as a VLSI Designer until January 2018. Subsequently, a position as Staff Design Engineer at Qualcomm was held until July 2020, followed by a role at Marvell Technology as Senior Staff ASIC Design Engineer and Principal Design Engineer from July 2020 to April 2023. Currently, Dima serves as a Senior RTL Design Engineer at Google since May 2025. Dima completed a Bachelor of Science degree in Electrical and Electronics Engineering at Tel Aviv University from 2008 to 2012.
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