Dor Shallev is a skilled engineer with extensive experience in ASIC design and verification. From October 2014 to May 2020, Dor worked at Mellanox Technologies as a Chip Design Engineer, focusing on ASIC logic design and functional verification. Subsequently, Dor took on the role of Chip Design Senior Engineer at NVIDIA from May 2020 to August 2022, specializing in ASIC logic design within the networking department and managing the networking management data unit for NVIDIA’s switch and GPU. Currently, Dor serves as an ASIC RTL Design Engineer at Google since August 2022. Dor holds a Bachelor's Degree in Education and Teaching from Lifshitz College of Education Jerusalem and a Bachelor of Science Degree in Electrical and Electronics Engineering from Bar-Ilan University.
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