Haemanth Subburaman is an experienced ASIC Design Verification Engineer currently at Google since November 2019. Previous roles include ASIC/Layout Design Engineer 2 at AMD from May 2018 to October 2019, responsible for RTL design and verification in video decoder pipelines, and ASIC Verification and Validation Intern at Infinera from May 2016 to April 2017, where verification test plans were executed and RTL code enhancements were implemented. Haemanth also held positions as an Undergraduate Research Assistant at McMaster University, contributing to a surveillance project, and served as a Teaching Assistant. An initial internship at Telecor Inc. focused on testing and troubleshooting analog circuits. Haemanth holds a Bachelor of Engineering in Electrical and Electronics Engineering with a Minor in Management, graduating Summa Cum Laude from McMaster University in 2017.
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