Harish Kumar Polepalli

Harish Kumar Polepalli is an experienced Layout Engineer and Standard Cell Layout Design Engineer with a demonstrated history of working in prominent technology companies including Intel Corporation, ARM Embedded Technologies, INVECAS, Google, SYNOPSYS, and Soctronics. With a strong background in layout design on various semiconductor technologies, Harish has expertise in working with lower technologies such as 14nm FinFET and 28nm CMOS. Harish holds a Bachelor's degree in Electronics and Communication Engineering from IETE New Delhi, a Diploma in Embedded Systems from the Government Institute of Electronics in A.P., and a Master of Technology in Microelectronics from BITS Pilani.