KT Sio

KT Sio has a robust background in engineering and design methodology, with experience from companies such as 台積電 (TSMC) and Google. KT Sio worked as a Senior Engineer at 台積電 from July 2012 to June 2016, focusing on technology benchmarking and performance metrics (FOM). Prior to that, KT Sio served as an Engineer at TSMC from September 2010 to June 2012. Currently, KT Sio holds the position of Design Methodology and IP Lead for Next Generation CPU at Google, responsible for RTL2GDS CAD, CPU design methodology, and various aspects of test chip implementation. KT Sio has a foundational education in Bio-industrial Mechatronics Engineering and Biomedical Electronics and Bioinformatics from National Taiwan University, complemented by advanced studies in law and an Executive MBA from Quantic School of Business and Technology.