LEE PING CHUA is an accomplished engineer with extensive experience in FPGA design and verification. At Intel Corporation from July 2017 to March 2025, LEE served as a Senior Staff FPGA Design Engineer, where contributions included the conceptualization and development of the first AXI-based extensible FPGA accelerator shell, aimed at enhancing custom platform creation for various market segments. Prior experience at Altera involved leading the design of the Stratix 10 Transceiver PHY IP and developing formal verification software for FPGA tools. Currently, LEE holds the position of Hardware Engineer at Google, focusing on TPU design. LEE holds a Master of Engineering in Microelectronics & Computer System and a Bachelor of Science in Computer Engineering, both from Universiti Teknologi Malaysia.
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