Mayank Verma

Mayank Verma is a VLSI RTL Design Engineer at Google, where they manage the design of the Memory subsystem engine for the Pixel mobile System on Chip. With 12 years of experience in the VLSI RTL Design domain, they have expertise in high-speed, high-performance pipelined design methodologies and a comprehensive understanding of various protocols and memory systems. Previously, Mayank worked as a Senior Engineer at Qualcomm and as a Design Engineer at AppliedMicro, where they contributed to high-performing mobile chipsets and multi-core SoC products. They also served as a Principal Design Engineer at Cadence Design Systems, focusing on DDR memory controller IP development. Mayank holds a Post Graduate Diploma in VLSI from CDAC-ACTS, Pune, and a Bachelor of Technology in Electronics and Communications Engineering from the Greater Noida Institute of Technology.