Ming Chi Lin

Ming Chi Lin has over two decades of experience in the electronics industry, with notable positions at MOAI Electronics Corporation as Director from June 2003 to April 2015, where responsibilities involved the development of High Speed Transceiver (USB3). Following that, Ming Chi Lin served as Chief Engineer at XunweiTech from February 2020 to July 2022, focusing on SERDES RX Circuit Design, specifically developing RX EQ Adaption Algorithms and building VerilogA models. Ming Chi Lin held the role of Manager at Faraday from April 2015 to February 2020, where responsibilities included overseeing Programmable 32G SERDES integration and various algorithm developments. Currently, Ming Chi Lin is a High Speed Interface Design Engineer at Google since December 2022. Ming Chi Lin holds a Master's Degree in Electronics Engineering from National Chiao Tung University, which was completed between 1998 and 2000.