Ming Mou

Ming Mou is an experienced engineer specializing in ASIC and FPGA design, with a professional career spanning several years in prominent technology companies. Ming began as an ASIC Design Engineer at Marvell Semiconductor from February 2013 to October 2016, followed by a role as FPGA Design Engineer III at F5 from October 2017 to September 2019, and progressing to Senior FPGA Design Engineer during that tenure. Subsequently, Ming worked as an FPGA Design Engineer at Aeva from January 2021 to March 2022. Since March 2022, Ming has been serving as an RTL Design Engineer at Google. Ming holds a Bachelor of Science from Nanjing University of Science and Technology (2007-2011) and a Master of Science from the University of Southern California (2011-2013).