Phaneendra Sagar

Phaneendra Sagar is a Design Verification Manager in Multimedia at Google, bringing over 11 years of experience in IP/Block level verification. They have developed constrained random verification environments using UVM-SV, executed formal verification with JasperGold and VC-Formal, and employed assertion-based and metric-driven verification methods. Prior to their current role, Phaneendra worked at Micron Technology as a Senior Engineer and Staff Engineer in ASIC Verification, and at Xilinx as a Member Of Technical Staff. They hold a Master of Technology in VLSI Design from C-DAC Mohali and a Bachelor of Technology in Electronics and Communication from Lakireddy Bali Reddy College of Engineering.