Piyush Kasera

Piyush Kasera is a Silicon RTL Design Engineer at Google, specializing in custom AI/ML silicon development for Google Cloud. They completed a Master of Science in Computer Engineering from the University of Southern California, where they maintained a GPA of 3.71. Piyush has over four years of experience in ASIC/FPGA RTL design and micro-architecture, having previously held roles at NVIDIA and Intel. They are well-versed in C/C++, Verilog, and System Verilog, and strive for excellence in their work while continually learning new design concepts and technologies.