Rajeev Varshney is an experienced engineer specializing in VLSI design and silicon design with a comprehensive background in digital design, design debug, synthesis, and static timing analysis. Rajeev began a career at Qualität Systems as a VLSI Design Engineer before advancing to Rudraksha Technology in the same role. Following this, Rajeev held the position of Lead Engineer at HCL Technologies and then served as an Advanced Consultant at Altran. From June 2019 to May 2022, Rajeev worked as a Senior Application Specific Integrated Circuit Design Engineer at Microchip Technology Inc. Currently, Rajeev is a Silicon Design Engineer at Google since June 2022. Rajeev holds a PG Diploma in VLSI from CDAC and an Engineer’s Degree in Electrical, Electronics and Communications Engineering from Dronacharya College of Engineering, Greater Noida.
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