Rajesh Kumar is a seasoned Silicon Engineer with extensive experience in ASIC physical design implementation spanning over a decade. Currently employed at Google since September 2020, Rajesh previously worked as a Design Engineer at Intel Corporation from February 2018 to August 2020, and as a Partition Execution Owner and Mentor at Infosys from February 2015 to November 2017. Rajesh has an impressive track record across various roles involving advanced mobile and communication designs, with significant responsibilities in mentoring junior engineers and overseeing complex projects. Educational qualifications include a Bachelor of Technology in Electronics Communication Engineering from Amrita School of Engineering. Rajesh also has notable experience interning at Bharat Electronics Limited, focusing on improving FPGA implementations in defense applications.
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