Sandeep Bhatia

Sandeep Bhatia is currently the DFx Lead for Google TPUs, where they focus on ASIC design with an emphasis on test, debug, reliability, and yield. Prior to this role, Sandeep held senior engineering positions at Cadence Design Systems and Oasys Design Systems, among other companies. They began their career as a Principal Engineer at Cross Check before transitioning to influential roles in product direction and architecture. Sandeep is also pursuing advanced degrees, including a Ph.D. from Princeton University and an M.S. from the University of Rochester, building on their B.Tech. from the Indian Institute of Technology, Delhi.