Sarin Thomas

Sarin Thomas is an accomplished engineer with extensive experience in hardware and ASIC architecture. Notable positions include Principal Engineer at Juniper Networks from May 2001 to January 2017, focusing on the architecture of next-generation ASICs for routing and switching, queuing, and fabric scheduling. Prior experience includes roles at HAL Computer Systems, where design verification of the SPARC64 V microprocessor was performed, and at First Virtual Communications as a Hardware Design Engineer responsible for FPGA and ATM switch interface card development. Sarin also worked at HCL Technologies on various design projects and is currently a Hardware Engineer at Google, contributing to technical infrastructure. Sarin holds a Master’s degree in Electrical Engineering from Stanford University and a Bachelor’s degree in Electronics and Communication Engineering from the National Institute of Technology Calicut.