Shabbir Saifee

Shabbir Saifee is currently a Lead Silicon Design Engineer at Google in Bangalore, specializing in full-chip timing closure and various aspects of silicon design including Logic Synthesis and Place & Route. Previously, Shabbir worked as a Physical Design Engineer at Intel Corporation from 2013 to 2023, where they also held the position of Lead STA/Senior Physical Design Engineer. Shabbir earned a Master of Technology (MTech) in VLSI Design from NIRMA University and a Bachelor of Engineering (BE) in Electrical, Electronics, and Communications Engineering from V.V.P. Engineering College, Rajkot.