Sharafali TP is an experienced RTL Design Engineer currently working at Google since October 2024. Prior positions include roles at Sony LSI Design Inc. from January 2018 to April 2019 and QuEST Global from June 2019 to October 2020, where Sharafali held the title of Senior RTL Design Engineer. Additional experience includes a tenure at Cerium Systems from October 2020 to October 2021 as a Senior RTL Design Engineer and at Intel Corporation from October 2021 to October 2024 as an IP Logic Design Engineer, focused on CXL IP development. Sharafali began the career at QuEST Global in February 2016. Educational qualifications include a Bachelor of Technology (BTech) in Applied Electronics and Instrumentation from the College of Engineering, Trivandrum, completed in 2015 with first-class honors.
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