Suhina Pal

ASIC Design Verification Engineer

Suhina Pal is currently an ASIC Design Verification Engineer at Google, a position held since 2022. Previously, Suhina worked as a Design Verification Engineer at Qualcomm from 2018 to 2022 and briefly as a Software Engineer 2 at Cisco in 2018. Suhina also served as a Teaching Assistant at BITS Pilani in 2017. Suhina holds a Master of Engineering from BITS Pilani and a Bachelor of Technology from the Heritage Institute of Technology, Kolkata.

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Bengaluru, India

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