Surabhi Patil is a highly skilled engineer with extensive experience in physical design and system-on-chip design, currently serving as a Physical Design Engineer at Google since October 2024. Previously, Surabhi worked at Tenstorrent Inc. as a Physical Design Engineer from December 2021 to October 2024, focusing on high-performance ARM IPs and utilizing Cadence and Synopsys tools. Prior to that, Surabhi held the role of System-on-Chip Design Engineer at Intel Corporation from February 2017 to December 2021, contributing to RTL development and synthesis for advanced technology nodes. Surabhi began the professional journey as an Embedded Engineer at Tata Technologies and also gained teaching experience as a Graduate Teaching Assistant at the University of Minnesota. Surabhi holds a Master’s Degree in Electrical and Electronics Engineering from the University of Minnesota-Twin Cities and a Bachelor of Technology in Electronics and Telecommunication from VIT Pune.
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