Sushma C. is a skilled engineer with experience in semiconductor design, currently serving as a Silicon Engineer at Google, specializing in standard cell layout for TSMC 2nm technology. Prior experience includes a temporary role as a Standard Cell Layout Engineer at Samsung Semiconductor and a Lead Engineer position at HCLTech focused on memory layout using FinFET technology. Sushma C. gained practical experience through an internship at FrenusTech Pvt Ltd, where expertise in standard cell layout design, analog layout, I/O layout, floor planning, and routing was developed. Educational qualifications include a Bachelor's degree in Electronics and Communication Engineering from S G Balekundri Institute of Technology.
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