Xiaoxiao Long has extensive experience in ASIC design engineering, holding the position of Sr. ASIC Design Engineer at Ambarella Inc from February 2015 to September 2018, followed by the role of ASIC RTL Engineer at Google since October 2018. Xiaoxiao Long obtained a Bachelor of Science in Electrical Engineering from Shanghai Jiao Tong University in 2013 and a Master of Science in Electrical Engineering from the University of California, Los Angeles in 2014.
This person is not in the org chart
This person is not in any teams
This person is not in any offices