Yash Asrani

Yash Asrani is an experienced engineer specializing in ASIC design verification, with a significant background in verification systems and methodologies. Yash began professional experience at Broadcom as an intern focusing on performance evaluation of RTL modules. Subsequently, Yash held various positions at Qualcomm, including Senior Design Verification Engineer, contributing to IO system coherency verification of PCIe subsystems and processors. At Google, Yash progressed from ASIC Design Verification Engineer to Senior ASIC Design Verification Engineer, ultimately becoming ASIC DV Technical Lead & Manager, leading core verification of the Edge TPU ML accelerator. Yash holds a Master's degree in Computer Engineering from North Carolina State University and a Bachelor's degree in Electronics and Telecommunication Engineering from Thadomal Shahani Engineering College, complemented by early education at S.I.E.S College of Arts, Science and Commerce and Little Angels' High School.