YiPing Su

YiPing Su is a Power/PMIC Architect at 谷歌 since April 2021, bringing extensive experience in analog circuit and power management design in SOC across various technology nodes, including 55nm, 40nm, 22nm, and 12nm. Prior to this role, YiPing Su worked at 聯詠科技股份有限公司 from 2015 to April 2020, serving as both Principal Engineer and Technical Manager, where responsibilities included pre-driver and power MOS design in FinFET processes and startup analysis methods for multiple solutions loops. YiPing Su holds a Bachelor's degree from 國立中山大學 and a Doctor of Philosophy in Electrical Engineering with a focus on IC design from 國立交通大學.