Albert Cheng

Albert Cheng is a seasoned engineer specializing in ASIC logic design, currently serving as a Senior ASIC Logic Design Engineer at Groq since May 2021. With a robust career trajectory that includes senior roles at Hewlett Packard Enterprise and Cray Inc., Cheng has extensive experience in designing high-performance computing architectures. Notably at Intel, Cheng contributed to the microarchitecture of the Omni-Path high-radix switch ASIC and various architectural features for HPC fabrics. Additional roles at companies like Cascade Design Automation and Ultrasonics Array reflect a diverse background in ASIC verification, software development, and hardware design. Cheng holds both a Master's and Bachelor's degree in Electrical Engineering from the University of Washington, completed between 1986 and 1991.