Chris Candler

Chris Candler has extensive work experience in various engineering roles. Chris currently serves as a Principal Engineer at Groq. Prior to that, they worked as a Sr. Principal Engineer at Ethernovia, where they were a member of the ASIC team involved in designing cutting-edge chips for the automotive industry. Chris also has experience as a Principal Engineer at Movellus Inc., where they focused on ASIC design. Additionally, Chris worked at Intel Corporation as a Principal Engineer, applying their ASIC Verilog hardware design experience to hardware design in OpenCL for an FPGA-based Deep Learning Accelerator core. Chris also has significant management experience as a Senior Manager of Design Engineering at Altera, where they oversaw three IP and Device software teams. Chris has held other positions such as Director of Engineering at Geo Semiconductor, Inc., System Architect at Fresco Microchip, and ASIC Design Manager at Silicon Optix. Chris began their career as a Design Engineer at Leitch Technology and Nortel Networks.

Chris Candler obtained a Bachelor of Engineering degree in Computer Engineering from McGill University in 1988. From 1988 to 1990, they pursued a Master's degree in Electrical, Electronics and Communications Engineering at the University of Maryland.