Leo Ye is an ASIC Engineer at Huawei Enterprise with over 13 years of experience focusing on FPGA and ASIC verification, specializing in EDA simulation. They have proficiency in C++ and SystemVerilog, as well as TCL scripting, and are well-versed in VMM/UVM methodologies. Leo previously served as a Verification Leader at Huawei Enterprise from 2001 to 2006 before becoming a Senior Engineer and Team Leader at 海思 in 2006. They earned a Bachelor's degree in Automation from 东北大学 in 2000.
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