Yichen Yang

Yichen Yang is a Design Verification Engineer at 海思, with prior experience as a Digital IC Design Engineer at Silicon Integrated Co., Ltd and as a Digital IC Intern at Innatera Nanosystems and 南京芯视界微电子科技有限公司. At Innatera Nanosystems, Yichen focused on high-speed and self-timed off-chip interconnect systems, specifically working on a ring topology at the behavioral level and optimizing system performance. Yichen's academic background includes a Master of Science in Electrical Engineering (Microelectronics track) from Delft University of Technology and a Bachelor's Degree in Electrical and Electronics Engineering from Chongqing University.