Yu Wang is an ASIC RTL designer and Assistant Engineer A at Hisilicon, where work involves developing DSS for the Kirin SoC since March 2016. Additionally, Yu Wang serves as a Graduate Research Assistant at Auburn University, focusing on metastability-immune timing-error detection circuit design using BTWC strategy and designing a timing-error detection sequential circuit in 45nm technology. Yu Wang holds a Master of Science in Electrical and Electronics Engineering from Auburn University (2012-2014) and a Bachelor of Science in Physics from Southeast University (2008-2012).
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