Kai Jiang

Kai (Kent) Jiang is an experienced Senior Engineer specializing in digital IC design and verification, currently employed at Huawei since 2017. They previously held positions at Synopsys from 2013 to 2017 as a Senior Supervisor and at Sunplus from 2006 to 2013 as a Department Manager. Kai has a strong background in telecommunications, with expertise in Universal Verification Methodology (UVM), SystemVerilog, and various aspects of synthesis and timing analysis. They obtained a Bachelor's degree in Computer Science and Technology from the National University of Defense Technology and a Master's degree in Electrical and Information Engineering from the University of Electronic Science and Technology of China.