Tom Rollet is a Senior Research Engineer specializing in CPU microarchitecture research and development, with a focus on frontend performance and efficiency. Previously, they held positions as a Simulation and Modelling Engineer at Huawei and an Intern in CPU Modelling. Before that, Tom worked as an Intern Modelling at Arm and conducted undergraduate research at LSE - EPITA Systems Laboratory. They completed their education at EPITA: Ecole d'Ingénieur en Informatique, following their studies at EPF Ecole d'Ingénieurs.
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