Zan Pay is a Senior Staff Engineer with extensive experience in the semiconductors industry, specializing as a Layout Lead Designer. They have demonstrated proficiency in layout editing using Cadence Virtuoso and automating processes with Cadence SKILL code to enhance efficiency. Zan has worked on various technology nodes, including 130nm to 7nm, focusing on library development for IO pad layout and SRAM. They hold a Master of Science in Nanoelectronics from the National University of Singapore and maintain a strong interest in tackling engineering challenges. Currently, Zan is employed as a System Architecture Engineer at Huawei.
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