Arvind Haran is a Senior Engineer at IBM, focusing on electronic design automation methodology design and tool development. Since February 2015, they have worked on verifying cache coherence for IBM's POWER architecture. Prior to joining IBM, Arvind was a graduate student at the University of Utah, where they developed symbolic techniques for soft-error resilience and approximate computation under Dr. Zvonimir Rakamaric. Their experience includes interning at Goldman Sachs, where they designed a protocol suite that significantly improved communication speed for an E-trading system, and they have held various research roles exploring advanced computational concepts. Arvind holds a Master's degree in Computer Science from the University of Utah and a Master's degree in Theoretical Computer Science from PSG College of Technology.
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