Jieming Qi

Jieming Qi is a Senior Analog Design Engineer at IBM, focusing on 50 Gbps SerDes PHY design using 7nm FinFET technology. Previously, Jieming worked at Everspin Technologies as a Mixed Signal Design Engineer, leading IO design for DDR SDRAM memory interfaces and performing signal integrity analysis. Jieming also served as a Senior IC Design Engineer at IBM for over a decade, where tasks included high-speed SerDes PHY design and PLL design for the CELL processor. Jieming holds a Ph.D. in Electrical Engineering from The University of Texas at Austin and a master's degree from the University of Notre Dame, along with a master's degree from the Beijing Institute of Technology.