Niraj Pandey is a Hardware Verification Engineer at IBM, specializing in the development of tools for pre/post silicon Power PC processor validation. They possess a deep understanding of Power PC processor architecture and operating system internals, along with strong system programming and debugging skills. Niraj has prior experience developing applications for the Cell Broadband Engine processor and is knowledgeable in a variety of programming languages, including C, C++, and Perl. They held several engineering positions at IBM from 2006 to 2014 and completed education at C-DAC Pune in 2006.
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