Raghava Madem

Raghava Madem is a Logic Design Engineer at IBM ISDL, with a strong background in digital design and RTL development. They have three years of experience in block/IP level RTL design, specializing in 4G/5G RFIC chips while previously working as an IP Design Engineer at Qualcomm. Raghava holds a Bachelor of Technology in Electronics and Communication Engineering from the National Institute of Technology, Patna, and a Master of Technology in Microelectronics and VLSI Design from the Indian Institute of Technology, Kharagpur. Their experience includes developing automated flows for design efficiency and contributing to cross-functional teams throughout the design process.