Joris Plessers

Joris Plessers is a Senior Digital Design Engineer at ICsense, where they focus on RTL design and FPGA validation. Joris previously worked as an Electronic Design Engineer at Layers NV and held roles as a Design Engineer and Senior Design Engineer at Barco Silex, specializing in cryptographic algorithms and verification. They completed a PhD research at KULeuven, exploring side channel attacks on cache memory during AES encryption, and have a strong academic background in electronics and cryptography from their studies at Sint-Jozefscollege Lommel and Katholieke Hogeschool Limburg.