Tim Paredaens is a Principal Digital Design Engineer at ICsense. They previously held the position of Senior Digital Design Engineer at the same company after working as a Design Engineer at ST-Ericsson from 1999 to 2012, where they focused on digital design, verification, and validation of SOC and IP designs. Tim holds a Master of Engineering in Electrical, Electronics, and Communications Engineering from Vrije Universiteit Brussel, which they completed in 1999.
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