Triveni T

Triveni T has a strong background in engineering, particularly in verification and design. Starting as an Internship Trainee at MosChip Institute of Silicon Systems (M-ISS) from November 2019 to September 2020, Triveni T gained foundational knowledge in Advanced VLSI Design and Verification concepts. Triveni T then served as a Design Verification Engineer at Atria Logic Inc. from October 2020 to April 2022, followed by a role as a Verification Engineer at Xilinx working on AMD Versal SOC verification until December 2021. Between May 2022 and December 2023, Triveni T worked as an Engineer at Qualcomm focusing on GPU block level verification using SV and UVM. Currently, since May 2025, Triveni T holds the position of Senior Hardware Engineer at Imagination Technologies, concentrating on block level verification of front-end GPU pipelines. Triveni T holds a Bachelor's degree in Electrical, Electronics and Communications Engineering from Lingaya's Institute of Management and Technology, completed in 2017.