Chen Wu

Chen Wu has extensive experience in interconnect technology, currently serving as Program Manager for the Nano-Interconnect Program at imec. Previously, they held positions as a Senior Researcher and R&D Engineer, focusing on process integration for CMOS BEOL. Their background includes a role as Staff Engineer in Memory Technology and Packaging Engineering at Western Digital and as Principal Engineer in Chipset Technology Planning at Huawei. Chen earned a Bachelor’s in Material Processing and Control Engineering from Huazhong University of Science and Technology, followed by a Master’s in Electrical Engineering from Chalmers University of Technology and a PhD in Materials Engineering from Katholieke Universiteit Leuven.