Jayati T. is a Senior DFT Engineer at Infineon Technologies, having previously held positions as an ASIC Design Engineer at NVIDIA and a Design Engineer 2 at AMD. Jayati worked on shift timing analysis and ATPG with DFT teams in past roles. They hold a Master of Technology in Electronics and Communication Engineering from the National Institute of Technology Warangal and a Bachelor of Engineering from Birla Institute of Technology, Mesra. Jayati's expertise is complemented by internship experience at Texas Instruments, where they learned about the deployment of analog circuits.
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