Michael Wagner is a seasoned professional with 21 years of expertise in physical design and implementation. Currently serving as the Senior Principal and Technical Lead of Physical Design and SoC Timing at Infineon Technologies, they excel in semi-custom, full-custom, mixed-signal, and analog design. Previously, they held significant roles at major companies such as Intel Corporation and Qimonda AG, where they demonstrated innovation by implementing a methodology change that reduced DRAM development time from 11 to 7 months. Michael's extensive skills include EDA expertise and a strong command of various design tools and methodologies, along with 16 patents in full custom and mixed signal design.
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