Jad Khatib

Jad Khatib is a Research Engineer at Inria since September 2019, focusing on the parallelization of real-time embedded systems within Many-core Architecture (MPPA3), with significant contributions to memory access modeling and architectural innovations. Previously, as a Research Engineer at Télécom Paris from September 2017 to September 2019, Khatib specialized in scheduling mixed-criticality systems on multi-core architecture. A Doctoral Student at CEA from May 2014 to September 2017, Khatib developed models and scheduling techniques for embedded real-time systems. An earlier role as a Teaching Assistant at Polytech Sorbonne involved teaching algorithmic and C programming courses. Khatib holds a PhD in Computer Science from Sorbonne Université, a Master's degree in Operations Research from Université de Bordeaux, and a Bachelor's degree in Pure Mathematics from Lebanese University.