Aditya .

Aditya is a Lead Design Verification Engineer at Intel, where they have developed validation components and verified debug IPs for servers and client PCs using OVM since 2024. Previously, they served as a Design Verification Engineer at Intel from 2019 to 2022. Aditya holds an M.Tech in Digital Techniques and Instrumentation from the Indian Institute of Technology (BHU) and a B.Tech in Electronics and Communication Engineering from Jaypee Institute of Information Technology. They achieved a 99.7 percentile in GATE 2017 and completed a dissertation on an Elliptic Curve Cryptography Processor in Verilog.