Cedric Villat is a Principal Engineer specializing in SOC and IP validation, with over 20 years of experience in the industry. They previously held the position of USB/XHCI Pre-Silicon Validation Architect at Intel from 2004 to 2019, where they led the architectural development and validation of complex USB IPs. Since 2019, they have served as a PCH SOC Pre-Silicon Validation Architect, driving innovation and technical strategy for a large team. Cedric holds a Bachelor's degree in Computer Engineering from California State University-Sacramento, earned in 2004.
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